1. Technical Field
The present invention relates to a test module and a test method. In particular, the present invention relates to a test module and a test method that can read, at high-speed, the number of fails accumulated for each channel and measured at any intervals.
2. Related Art
Patent Document 1, for example, describes a test apparatus that can decrease testing time for a memory under test that has a repair block for every region. This test apparatus includes a pattern generator that generates a test pattern or the like to be supplied to the memory under test; a logic comparator that compares (i) an output signal output from the memory under test in response to the test pattern to (ii) an expected value signal, and outputs fail data if the output signal does not match the expected value signal; and a plurality of fail counters that count the pieces of fail data for the output signal from the memory under test.    Patent Document 1: Japanese Patent Application Publication No. 2006-012253
A conventional test apparatus includes a plurality of fail counters for counting the number of fails, as described above. However, the fail counts by the fail counters are acquired in a pattern burst containing a plurality of continuous test patterns and the values of the fail counters are read after the pattern burst is finished, thereby obtaining the number of fails in this pattern burst. Accordingly, in order to obtain the number of fails in each test pattern, the data in a fail memory that records the presence of fails in time sequence is used. For example, the number of fails in a certain test pattern can be obtained by reading the data from the fail memory corresponding to this test pattern and processing the read data using a data processing apparatus operating according to software. Since the reading and processing of the fail data happens after the testing, the overall testing time is increased.
Furthermore, when calculating the error rate for each test pattern, it is necessary to know the number of patterns undergoing logic comparison. If the data stored in the fail memory is processed after the testing to calculate the error rate, it is necessary to store all of the data of the logic comparisons in the fail memory, thereby increasing the capacity needed for the fail memory. In other words, the sampling intervals of the logic comparisons depend on the capacity of the fail memory, resulting in long sampling intervals if the fail memory has low capacity.